An important aspect of semiconductor fabrication is the testing of circuit structures to insure that design specifications are met and for isolating sources of defects in the wafer processing. In general, testing each layer or fabrication step during fabrication has been impractical. Because of the time and expense involved, only limited in-process testing is possible. The available in-process testing methods provide only limited information which is both untimely and inadequate. In particular, the prior art methods do not provide information on the defect density (i.e., the percentage of failed devices on the chip). Circuit testing structures performed on the circuit after complete fabrication give even more limited information on processing and design errors because it is difficult to determine the level on which the error occurred.
One prior method of testing comprises placing a comb-like test structure having interleaving tines and integral probe pads on the semiconductor wafer. The test structure is built during the integrated circuit fabrication or on a separate pilot wafer and reflects the structures and intricacy required therein. Once the integrated circuit is completed, a mechanical probe testing device is used to contact the probe pads on the test structure and an electrical readout is obtained. The readout provides little more than a pass/fail indication with no fault location information. Additionally, the use of a mechanical probe testing device requires the use of probe pads for contact between the test structure and the probes. Since the probe pads often require significantly more space than the test structure itself due to the size of the probes, there is an inherent wasting of valuable wafer surface space.
Another test architecture is described in U.S. patent Ser. No. 327,080 to Mahant Shetti et al., filed Mar. 22, 1989, now U.S. Pat. No. 4,978,908, entitled "Scanning Electron Microscope Based Parametric Testing Method and Apparatus," which is incorporated by reference herein. In this test architecture, a scanning electron microscope produces an electron beam which is aimed at a test structure comprising a plurality of islands formed within a grid of structure. Secondary electrons emitted from the islands are displayed on a monitor. This information can detect whether the island is electrically separated from the grid or shorted thereto by comparing the intensity of the secondary electrons emitted from the islands.
While this test system is very effective, it is limited in the test data which may be obtained on structures over which a material layer, such as an oxide layer, has been formed.
Therefore, a need has arisen in the industry for a test method and apparatus which may accurately test integrated circuits design specifications during fabrication.